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USB3280
Hi-Speed USB Device PHY with UTMI Interface
PRODUCT FEATURES
Available in a 36-pin lead-free RoHS compliant (6 x 6 x 0.90mm) QFN package Interface compliant with the UTMI specification (60MHz, 8-bit bidirectional interface) Only one required power supply (+3.3V) USB-IF "Hi-Speed" certified to USB2.0 electrical specification Supports 480Mbps Hi-Speed (HS) and 12Mbps Full Speed (FS) serial data transmission rates Integrated 45 and 1.5k termination resistors reduce external component count Internal short circuit protection of DP and DM lines On-chip oscillator operates with low cost 24MHz crystal Latch-up performance exceeds 150mA per EIA/JESD 78, Class II ESD protection levels of 5kV HBM without external protection devices SYNC and EOP generation on transmit packets and detection on receive packets NRZI encoding and decoding Bit stuffing and unstuffing with error detection
Datasheet Supports the USB suspend state, HS detection, HS Chirp, Reset and Resume Support for all test modes defined in the USB 2.0 specification 55mA Unconfigured Current (typical) - ideal for bus powered applications. 83uA suspend current (typical) - ideal for battery powered applications. Industrial Operating Temperature -40oC to +85oC APPLICATIONS The USB3280 is the ideal companion to any ASIC, SoC or FPGA solution designed with a UTMI Hi-Speed USB device (peripheral) core. The USB3280 is well suited for: Cell Phones MP3 Players Scanners External Hard Drives Digital Still and Video Cameras Portable Media Players
SMSC USB3280
DATASHEET
Revision 1.2 (10-27-06)
Hi-Speed USB Device PHY with UTMI Interface Datasheet
ORDER NUMBER(S): USB3280-AEZG FOR 36-PIN, QFN PACKAGE (LEAD-FREE ROHS COMPLIANT)
80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123 Copyright (c) 2006 SMSC or its subsidiaries. All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC's website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems Corporation ("SMSC"). Product names and company names are the trademarks of their respective holders. SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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SMSC USB3280
Hi-Speed USB Device PHY with UTMI Interface Datasheet
Table of Contents
Chapter 1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1 Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Chapter 2 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Chapter 3 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Chapter 4 Interface Signal Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Chapter 5 Limiting Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Chapter 6 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6.1 6.2 Driver Characteristics of Full-Speed Drivers in High-Speed Capable Transceivers . . . . . . . . . . . . 16 High-speed Signaling Eye Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Chapter 7 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.1 7.2 7.3 7.4 7.5 7.6 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock and Data Recovery Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TX Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RX Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . USB 2.0 Transceiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.6.1 High Speed and Full Speed Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.6.2 Termination Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.6.3 Bias Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Crystal Oscillator and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Regulators and POR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.8.1 Internal Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.8.2 Power On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 21 22 22 23 26 26 26 27 27 27 27 27
7.7 7.8
Chapter 8 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.11 8.12 8.13 8.14 Linestate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OPMODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Mode Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SE0 Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Suspend Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HS Detection Handshake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HS Detection Handshake - FS Downstream Facing Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HS Detection Handshake - HS Downstream Facing Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HS Detection Handshake - Suspend Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Assertion of Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Detection of Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HS Device Attach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 29 29 30 30 31 32 32 34 36 38 39 39 41
Chapter 9 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
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Hi-Speed USB Device PHY with UTMI Interface Datasheet
List of Figures
Figure 2.1 Figure 3.1 Figure 3.2 Figure 6.1 Figure 6.2 Figure 6.3 Figure 6.4 Figure 6.5 Figure 7.1 Figure 7.2 Figure 7.3 Figure 7.4 Figure 7.5 Figure 7.6 Figure 7.7 Figure 8.1 Figure 8.2 Figure 8.3 Figure 8.4 Figure 8.5 Figure 8.6 Figure 8.7 Figure 8.8 Figure 8.9 Figure 9.1 USB3280 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 USB3280 Pinout - Top View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 USB3280 Pinout - Bottom View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Full-Speed Driver VOH/IOH Characteristics for High-speed Capable Transceiver . . . . . . . . 17 Full-Speed Driver VOL/IOL Characteristics for High-speed Capable Transceiver. . . . . . . . . 17 Eye Pattern Measurement Planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Eye Pattern for Transmit Waveform and Eye Pattern Definition . . . . . . . . . . . . . . . . . . . . . . 19 Eye Pattern for Receive Waveform and Eye Pattern Definition . . . . . . . . . . . . . . . . . . . . . . . 20 FS CLK Relationship to Transmit Data and Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . 21 FS CLK Relationship to Receive Data and Control Signals. . . . . . . . . . . . . . . . . . . . . . . . . . 22 Transmit Timing for a Data Packet. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Receive Timing for Data with Unstuffed Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Receive Timing for a Handshake Packet (no CRC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Receive Timing for Setup Packet. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Receive Timing for Data Packet (with CRC-16). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Reset Timing Behavior (HS Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Suspend Timing Behavior (HS Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 HS Detection Handshake Timing Behavior (FS Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Chirp K-J-K-J-K-J Sequence Detection State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 HS Detection Handshake Timing Behavior (HS Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 HS Detection Handshake Timing Behavior from Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Resume Timing Behavior (HS Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Device Attach Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 USB3280 Application Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 USB3280-AEZG 36-Pin QFN Package Outline and Parameters, 6 x 6 x 0.90 mm Body (LeadFree RoHS Compliant) 42
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Hi-Speed USB Device PHY with UTMI Interface Datasheet
List of Tables
Table 4.1 System Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 4.2 Data Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 4.3 USB I/O Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 4.4 Biasing and Clock Oscillator Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 4.5 Power and Ground Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 5.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 5.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 5.3 Recommended External Clock Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 6.1 Electrical Characteristics: Supply Pins (Note 6.1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 6.2 DC Electrical Characteristics: Logic Pins (Note 6.2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 6.3 DC Electrical Characteristics: Analog I/O Pins (DP/DM) (Note 6.3) . . . . . . . . . . . . . . . . . . . . 14 Table 6.4 Dynamic Characteristics: Analog I/O Pins (DP/DM) (Note 6.4) . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 6.5 Dynamic Characteristics: Digital UTMI Pins (Note 6.5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 7.1 DP/DM termination vs. Signaling Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 8.1 Linestate States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 8.2 Operational Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 8.3 USB 2.0 Test Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 8.4 Reset Timing Values (HS Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 8.5 Suspend Timing Values (HS Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 8.6 HS Detection Handshake Timing Values (FS Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 8.7 Reset Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 8.8 HS Detection Handshake Timing Values from Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 8.9 Resume Timing Values (HS Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 8.10 Attach and Reset Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
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Chapter 1 General Description
The USB3280 provides the Physical Layer (PHY) interface to a USB 2.0 Device Controller. The IC is available in a 36-pin lead-free RoHS compliant QFN package.
1.1
Product Description
The USB3280 is an industrial temperature USB 2.0 physical layer transceiver (PHY) integrated circuit. SMSC's proprietary technology results in low power dissipation, which is ideal for building a bus powered USB 2.0 peripheral. The PHY uses an 8-bit bidirectional parallel interface, which complies with the USB Transceiver Macrocell Interface (UTMI) specification. It supports 480Mbps transfer rate, while remaining backward compatible with USB 1.1 legacy protocol at 12Mbps. All required termination and 5.25V short circuit protection of the DP/DM lines are internal to the chip. The USB3280 also has an integrated 1.8V regulator so that only a 3.3V supply is required. While transmitting data, the PHY serializes data and generates SYNC and EOP fields. It also performs needed bit stuffing and NRZI encoding. Likewise, while receiving data, the PHY de-serializes incoming data, stripping SYNC and EOP fields and performs bit un-stuffing and NRZI decoding.
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Hi-Speed USB Device PHY with UTMI Interface Datasheet
Chapter 2 Functional Block Diagram
XO
XI
PWR Control
VDD3.3
1.8V Regulator
TX LOGIC
TX State Machine Parallel to Serial Conversion Bit Stuff NRZI Encode
PLL and XTAL OSC
System Clocking
TX
RPU_EN 1.5k VPO VMO OEB HS_DATA HS_DRIVE_ENABLE HS_CS_ENABLE FS TX
RESET SUSPENDN XCVRSELECT TERMSELECT
OPMODE[1:0]
HS TX DP
LINESTATE[1:0] CLKOUT
R X
DM
UTMI Interface
RX LOGIC
RX State Machine Serial to Parallel Conversion Bit Unstuff VP VM
FS SE+
DATA[7:0]
TXVALID
TXREADY
FS SE-
Clock Recovery Unit
Clock and Data Recovery Elasticity Buffer FS RX MUX
RXVALID RXACTIVE RXERROR
NRZI Decode
HS RX
BIASING
Bandgap Voltage Reference Current Reference HS SQ
Figure 2.1 USB3280 Block Diagram
SMSC USB3280
RBIAS
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Chapter 3 Pinout
36
35
34
33
32
31
30
29
28
RXERROR
VDDA1.8
VDD3.3
VDD3.3
VDD1.8
VDD3.3
RBIAS
XO
XI
XCVRSELECT TERMSELECT TXREADY SUSPENDN TXVALID RESET VDD3.3 DP DM
1 2 3 4 5 6 7 8 9
27 26 25 24 23 22 21 20 19
RXVALID DATA[0] DATA[1] DATA[2] DATA[3] DATA[4] DATA[5] DATA[6] DATA[7]
USB2.0 USB3280 PHY IC
10 11 12 13 14 15 16 LINESTATE0 17 VDD1.8
OPMODE1
OPMODE0
LINESTATE1
VDD3.3
RXACTIVE
Figure 3.1 USB3280 Pinout - Top View
EXPOSED GND PAD
Figure 3.2 USB3280 Pinout - Bottom View The flag of the QFN package must be connected to ground.
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CLKOUT
VDD3.3
18
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Hi-Speed USB Device PHY with UTMI Interface Datasheet
Chapter 4 Interface Signal Definition
Table 4.1 System Interface Signals ACTIVE LEVEL High
NAME RESET (RST)
DIRECTION Input
DESCRIPTION Reset. Reset all state machines. After coming out of reset, must wait 5 rising edges of clock before asserting TXValid for transmit. Assertion of Reset: May be asynchronous to CLKOUT De-assertion of Reset: Must be synchronous to CLKOUT Transceiver Select. This signal selects between the FS and HS transceivers: 0: HS transceiver enabled 1: FS transceiver enabled. Termination Select. This signal selects between the FS and HS terminations: 0: HS termination enabled 1: FS termination enabled Suspend. Places the transceiver in a mode that draws minimal power from supplies. Shuts down all blocks not necessary for Suspend/Resume operation. While suspended, TERMSELECT must always be in FS mode to ensure that the 1.5k pull-up on DP remains powered. 0: Transceiver circuitry drawing suspend current 1: Transceiver circuitry drawing normal current System Clock. This output is used for clocking receive and transmit parallel data at 60MHz. Operational Mode. These signals select between the various operational modes: [1] [0] Description 0 0 0: Normal Operation 0 1 1: Non-driving (all terminations removed) 1 0 2: Disable bit stuffing and NRZI encoding 1 1 3: Reserved Line State. These signals reflect the current state of the USB data bus in FS mode, with [0] reflecting the state of DP and [1] reflecting the state of DM. When the device is suspended or resuming from a suspended state, the signals are combinatorial. Otherwise, the signals are synchronized to CLKOUT. [1] [0] Description 0 0 0: SE0 0 1 1: J State 1 0 2: K State 1 1 3: SE1
XCVRSELECT (XSEL)
Input
N/A
TERMSELECT (TSEL)
Input
N/A
SUSPENDN (SPDN)
Input
Low
CLKOUT (CLK) OPMODE[1:0] (OM1) (OM0)
Output Input
Rising Edge N/A
LINESTATE[1:0] (LS1) (LS0)
Output
N/A
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Table 4.2 Data Interface Signals ACTIVE LEVEL High
NAME DATA[7:0] (D7) . . . (D0) TXVALID (TXV)
DIRECTION Bidirectional
DESCRIPTION Data bus. 8-bit Bidirectional mode. TXVALID 0 1 DATA[7:0] output input
Input
High
Transmit Valid. Indicates that the DATA bus is valid for transmit. The assertion of TXVALID initiates the transmission of SYNC on the USB bus. The negation of TXVALID initiates EOP on the USB. Control inputs (OPMODE[1:0], TERMSELECT,XCVRSELECT) must not be changed on the de-assertion or assertion of TXVALID. The PHY must be in a quiescent state when these inputs are changed.
TXREADY (TXR)
Output
High
Transmit Data Ready. If TXVALID is asserted, the SIE must always have data available for clocking into the TX Holding Register on the rising edge of CLKOUT. TXREADY is an acknowledgement to the SIE that the transceiver has clocked the data from the bus and is ready for the next transfer on the bus. If TXVALID is negated, TXREADY can be ignored by the SIE. Receive Data Valid. Indicates that the DATA bus has received valid data. The Receive Data Holding Register is full and ready to be unloaded. The SIE is expected to latch the DATA bus on the rising edge of CLKOUT. Receive Active. Indicates that the receive state machine has detected Start of Packet and is active. Receive Error. 0: Indicates no error. 1: Indicates a receive error has been detected. This output is clocked with the same timing as the receive DATA lines and can occur at anytime during a transfer.
RXVALID (RXV)
Output
High
RXACTIVE (RXA) RXERROR (RXE)
Output Output
High High
Table 4.3 USB I/O Signals ACTIVE LEVEL N/A N/A USB Positive Data Pin. USB Negative Data Pin.
NAME DP DM
DIRECTION I/O I/O
DESCRIPTION
Table 4.4 Biasing and Clock Oscillator Signals ACTIVE LEVEL N/A
NAME RBIAS (RB) XI/XO
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DIRECTION Input
DESCRIPTION External 1% bias resistor. Requires a 12k resistor to ground. Used for setting HS transmit current level and on-chip termination impedance. External crystal. 24MHz crystal connected from XI to XO.
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Input
N/A
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Table 4.5 Power and Ground Signals ACTIVE LEVEL N/A High
NAME VDD3.3 (V33) REG_EN (REN)
DIRECTION N/A Input
DESCRIPTION 3.3V Supply. Provides power for USB 2.0 Transceiver, UTMI+ Digital, Digital I/O, and Regulators. On-Chip 1.8V regulator enable. Connect to ground to disable on chip VDDA1.8V and VDD1.8V regulators. When regulators are disabled, external 1.8V must be supplied to VDDA1.8 and VDD1.8 pins. 1.8V Digital Supply. Supplied by On-Chip Regulator when REG_EN is active. Low ESR 4.7uF minimum capacitor requirement when using internal regulators. Common Ground. 1.8V Analog Supply. Supplied by On-Chip Regulator when REG_EN is active. Low ESR 4.7uF minimum capacitor requirement when using internal regulators.
VDD1.8 (V18) VSS (GND) VDDA1.8 (V18A)
N/A
N/A
N/A N/A
N/A N/A
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Chapter 5 Limiting Values
Table 5.1 Absolute Maximum Ratings PARAMETER Maximum DP and DM voltage to Ground Maximum VDD1.8 and VDDA1.8 voltage to Ground Maximum 3.3V Supply Voltage to Ground Maximum I/O Voltage to Ground Storage Temperature ESD PERFORMANCE All Pins LATCH-UP PERFORMANCE All Pins ILTCH_UP EIA/JESD 78, Class II 150 mA VHBM Human Body Model 5 kV SYMBOL VMAX_5V VMAX_1.8V VMAX_3.3V VI TSTG CONDITIONS MIN -0.3 -0.3 -0.3 -0.3 -55 TYP MAX 5.5 2.5 4.0 4.0 150 UNITS V V V V
oC
Note: In accordance with the Absolute Maximum Rating system (IEC 60134)
Table 5.2 Recommended Operating Conditions PARAMETER 3.3V Supply Voltage (VDD3.3 and VDDA3.3) Input Voltage on Digital Pins Input Voltage on Analog I/O Pins (DP, DM) Ambient Temperature SYMBOL VDD3.3 VI VI(I/O) TA CONDITIONS MIN 3.0 0.0 0.0 -40 TYP 3.3 MAX 3.6 VDD3.3 VDD3.3 85 UNITS V V V
o
C
Table 5.3 Recommended External Clock Conditions PARAMETER System Clock Frequency System Clock Duty Cycle SYMBOL CONDITIONS XO driven by the external clock; and no connection at XI XO driven by the external clock; and no connection at XI 45 MIN TYP 24 (100ppm) 50 55 MAX UNITS MHz %
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Chapter 6 Electrical Characteristics
Table 6.1 Electrical Characteristics: Supply Pins (Note 6.1) PARAMETER Unconfigured Current FS Idle Current FS Transmit Current FS Receive Current HS Idle Current HS Transmit Current HS Receive Current Low Power Mode SYMBOL IAVG(UCFG) IAVG(FS) IAVG(FSTX) IAVG(FSRX) IAVG(HS) IAVG(HSTX) IAVG(HSRX) IDD(LPM) CONDITIONS Device Unconfigured FS idle not data transfer FS current during data transmit FS current during data receive FS idle not data transfer FS current during data transmit FS current during data receive VBUS 15k pull-down and 1.5k pull-up resistor currents not included. MIN TYP 55 55 60.5 57.5 60.6 62.4 61.5 83 MAX UNITS mA mA mA mA mA mA mA uA
Note 6.1
VDD3.3 = 3.0 to 3.6V; VSS = 0V; TA = -40oC to 85oC; unless otherwise specified.
Table 6.2 DC Electrical Characteristics: Logic Pins (Note 6.2) PARAMETER Low-Level Input Voltage High-Level Input Voltage Low-Level Output Voltage High-Level Output Voltage Input Leakage Current Pin Capacitance Note 6.2 SYMBOL VIL VIH VOL VOH ILI Cpin IOL = 8mA IOH = -8mA VDD3.3 - 0.5 1 4 CONDITIONS MIN VSS 2.0 TYP MAX 0.8 VDD3.3 0.4 UNITS V V V V uA pF
VDD3.3 = 3.0 to 3.6V; VSS = 0V; TA = -40oC to 85oC; unless otherwise specified.
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Table 6.3 DC Electrical Characteristics: Analog I/O Pins (DP/DM) (Note 6.3) PARAMETER FS FUNCTIONALITY Input levels Differential Receiver Input Sensitivity Differential Receiver Common-Mode Voltage Single-Ended Receiver Low Level Input Voltage Single-Ended Receiver High Level Input Voltage Single-Ended Receiver Hysteresis Output Levels Low Level Output Voltage High Level Output Voltage VFSOL VFSOH Pull-up resistor on DP; RL = 1.5k to VDD3.3 Pull-down resistor on DP, DM; RL = 15k to GND 2.8 0.3 3.6 V V VDIFS VCMFS VILSE VIHSE VHYSSE 2.0 0.050 0.150 | V(DP) - V(DM) | 0.2 0.8 2.5 0.8 V V V V V SYMBOL CONDITIONS MIN TYP MAX UNITS
Termination Driver Output Impedance for HS and FS Input Impedance Pull-up Resistor Impedance Pull-up Resistor Impedance Termination Voltage For Pullup Resistor On Pin DP HS FUNCTIONALITY Input levels HS Differential Input Sensitivity HS Data Signaling Common Mode Voltage Range HS Squelch Detection Threshold (Differential) Output Levels High Speed Low Level Output Voltage (DP/DM referenced to GND) VHSOL 45 load -10 10 mV VDIHS VCMHS VHSSQ Squelch Threshold Unsquelch Threshold 150 | V(DP) - V(DM) | 100 -50 500 100 mV mV mV mV ZHSDRV ZINP ZPU ZPURX VTERM Steady state drive (See Figure 6.1) TX, RPU disabled Bus Idle Device Receiving 40.5 10 0.900 1.425 3.0 1.24 2.26 1.575 3.09 3.6 45 49.5 M k k V
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Table 6.3 DC Electrical Characteristics: Analog I/O Pins (DP/DM) (Note 6.3) (continued) PARAMETER High Speed High Level Output Voltage (DP/DM referenced to GND) High Speed IDLE Level Output Voltage (DP/DM referenced to GND) Chirp-J Output Voltage (Differential) Chirp-K Output Voltage (Differential) Leakage Current OFF-State Leakage Current Port Capacitance Transceiver Input Capacitance Note 6.3 CIN Pin to GND 5 10 pF ILZ 1 uA SYMBOL VHSOH CONDITIONS 45 load MIN 360 TYP MAX 440 UNITS mV
VOLHS
45 load
-10
10
mV
VCHIRPJ
HS termination resistor disabled, pull-up resistor connected. 45 load. HS termination resistor disabled, pull-up resistor connected. 45 load.
700
1100
mV
VCHIRPK
-900
-500
mV
VDD3.3 = 3.0 to 3.6V; VSS = 0V; TA = -40oC to 85oC; unless otherwise specified.
Table 6.4 Dynamic Characteristics: Analog I/O Pins (DP/DM) (Note 6.4) PARAMETER FS Output Driver Timing Rise Time Fall Time Output Signal Crossover Voltage Differential Rise/Fall Time Matching HS Output Driver Timing Differential Rise Time Differential Fall Time Driver Waveform Requirements High Speed Mode Timing Receiver Waveform Requirements Data Source Jitter and Receiver Jitter Tolerance Note 6.4
SMSC USB3280
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
TFSR TFFF VCRS FRFM
CL = 50pF; 10 to 90% of |VOH - VOL| CL = 50pF; 10 to 90% of |VOH - VOL| Excluding the first transition from IDLE state Excluding the first transition from IDLE state
4 4 1.3 90
20 20 2.0 111.1
ns ns V %
THSR THSF Eye pattern of Template 1 in USB 2.0 specification
500 500 See Figure 6.2
ps ps
Eye pattern of Template 4 in USB 2.0 specification Eye pattern of Template 4 in USB 2.0 specification
See Figure 6.2 See Figure 6.2
VDD3.3 = 3.0 to 3.6V; VSS = 0V; TA = -40oC to 85oC; unless otherwise specified.
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Table 6.5 Dynamic Characteristics: Digital UTMI Pins (Note 6.5) PARAMETER UTMI Timing DATA[7:0] RXVALID RXACTIVE RXERROR LINESTATE[1:0] TXREADY DATA[7:0] TXVALID OPMODE[1:0] XCVRSELECT TERMSELECT DATA[7:0] TXVALID OPMODE[1:0] XCVRSELECT TERMSELECT Note 6.5 VDD3.3 = 3.0 to 3.6V; VSS = 0V; TA = -40oC to 85oC; unless otherwise specified. TH Hold time. Measured from the rising egde of CLKOUT to the PHY input signal edge. 0 ns TSU Setup Time. Measured from PHY input to the rising edge of CLKOUT. 5 ns TPD Output Delay. Measured from PHY output to the rising edge of CLKOUT 2 5 ns SYMBOL CONDITIONS MIN TYP MAX UNITS
6.1
Driver Characteristics of Full-Speed Drivers in High-Speed Capable Transceivers
The USB3280 uses a differential output driver to drive the USB data signal onto the USB cable. Figure 6.1 Full-Speed Driver VOH/IOH Characteristics for High-speed Capable Transceiveron page 17 shows the V/I characteristics for a full-speed driver which is part of a high-speed capable transceiver. The normalized V/I curve for the driver must fall entirely inside the shaded region. The V/I region is bounded by the minimum driver impedance above (40.5 Ohm) and the maximum driver impedance below (49.5 Ohm). The output voltage must be within 10mV of ground when no current is flowing in or out of the pin.
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Iout (mA)
-6.1 * |VOH|
Drive High Slope = 1/49.5 Ohm
-10.71 * |VOH|
Test Limit
Slope = 1/40.5 Ohm
0 0
0.566*VOH
0.698*VOH
VOH
Vout (Volts)
Figure 6.1 Full-Speed Driver VOH/IOH Characteristics for High-speed Capable Transceiver
Drive Low Iout (mA)
10.71 * |VOH|
Slope = 1/40.5 Ohm
Test Limit
22
Slope = 1/49.5 Ohm
0 0 1.09V 0.434*VOH
Vout (Volts)
VOH
Figure 6.2 Full-Speed Driver VOL/IOL Characteristics for High-speed Capable Transceiver
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6.2
High-speed Signaling Eye Patterns
High-speed USB signals are characterized using eye patterns. For measuring the eye patterns 4 points have been defined (see Figure 6.3). The Universal Serial Bus Specification Rev.2.0 defines the eye patterns in several `templates'. The two templates that are relevant to the PHY are shown below.
TP1 TP2
TP3
TP4
Traces
USB Cable
Traces
Transceiver
A Connector
B Connector
Transceiver
Hub Circuit Board
Device Circuit Board
Figure 6.3 Eye Pattern Measurement Planes
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The eye pattern in Figure 6.4 defines the transmit waveform requirements for a hub (measured at TP2 of Figure 6.3) or a device without a captive cable (measured at TP3 of Figure 6.3). The corresponding signal levels and timings are given in table below. Time is specified as a percentage of the unit interval (UI), which represents the nominal bit duration for a 480 Mbit/s transmission rate.
Level 1 400mV Differential
Point 3
Point 4
Point 1
Point 2
0 Volts Differential
Point 5 Level 2 0%
Point 6
-400mV Differential
Unit Interval
100%
Figure 6.4 Eye Pattern for Transmit Waveform and Eye Pattern Definition
VOLTAGE LEVEL (D+, D-) Level 1 Level 2 Point 1 Point 2 Point 3 Point 4 Point 5 Point 6 525mV in UI following a transition, 475mV in all others -525mV in UI following a transition, -475mV in all others 0V 0V 300mV 300mV -300mV -300mV
TIME (% OF UNIT INTERVAL) N/A N/A 7.5% UI 92.5% UI 37.5% UI 62.5% UI 37.5% UI 62.5% UI
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The eye pattern in Figure 6.5 defines the receiver sensitivity requirements for a hub (signal applied at test point TP2 of Figure 6.3) or a device without a captive cable (signal applied at test point TP3 of Figure 6.3). The corresponding signal levels and timings are given in the table below. Timings are given as a percentage of the unit interval (UI), which represents the nominal bit duration for a 480 Mbit/s transmission rate.
Level 1 400mV Differential Point 3 Point 4 0 Volt Differential
Point 1
Point 2
Point 5
Point 6
-400mV Differential Level 2 0% 100%
Figure 6.5 Eye Pattern for Receive Waveform and Eye Pattern Definition
VOLTAGE LEVEL (D+, D-) Level 1 Level 2 Point 1 Point 2 Point 3 Point 4 Point 5 Point 6 575mV -575mV 0V 0V 150mV 150mV -150mV -150mV
TIME (% OF UNIT INTERVAL) N/A N/A 15% UI 85% UI 35% UI 65% UI 35% UI 65% UI
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Chapter 7 Functional Overview
Figure 2.1 on page 7 shows the functional block diagram of the USB3280. Each of the functions is described in detail below.
7.1
Modes of Operation
The USB3280 supports an 8-bit bi-directional parallel interface. CLKOUT runs at 60MHz The 8-bit data bus (DATA[7:0]) is used for transmit when TXVALID = 1 The 8-bit data bus (DATA[7:0]) is used for receive when TXVALID = 0
7.2
System Clocking
This block connects to either an external 24MHz crystal or an external clock source and generates a 480MHz multi-phase clock. The clock is used in the CRC block to over-sample the incoming received data, resynchronize the transmit data, and is divided down to 60MHz (CLKOUT) which acts as the system byte clock. The PLL block also outputs a clock valid signal to the other parts of the transceiver when the clock signal is stable. All UTMI signals are synchronized to the CLKOUT output. The behavior of the CLKOUT is as follows: Produce the first CLKOUT transition no later than 5.6ms after negation of SUSPENDN. The CLKOUT signal frequency error is less than 10% at this time. The CLKOUT signal will fully meet the required accuracy of 500ppm no later than 1.4ms after the first transition of CLKOUT. In HS mode there is one CLKOUT cycle per byte time. The frequency of CLKOUT does not change when the PHY is switched between HS to FS modes. In FS mode there are 5 CLKOUT cycles per FS bit time, typically 40 CLKOUT cycles per FS byte time. If a received byte contains a stuffed bit then the byte boundary can be stretched to 45 CLKOUT cycles, and two stuffed bits would result in a 50 CLKOUT cycles. Figure 7.1 shows the relationship between CLKOUT and the transmit data transfer signals in FS mode. TXREADY is only asserted for one CLKOUT per byte time to signal the SIE that the data on the DATA lines has been read by the PHY. The SIE may hold the data on the DATA lines for the duration of the byte time. Transitions of TXVALID must meet the defined setup and hold times relative to CLKOUT.
Figure 7.1 FS CLK Relationship to Transmit Data and Control Signals
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Figure 7.2 shows the relationship between CLKOUT and the receive data control signals in FS mode. RXACTIVE "frames" a packet, transitioning only at the beginning and end of a packet. However transitions of RXVALID may take place any time 8 bits of data are available. Figure 7.1 also shows how RXVALID is only asserted for one CLKOUT cycle per byte time even though the data may be presented for the full byte time. The XCVRSELECT signal determines whether the HS or FS timing relationship is applied to the data and control signals.
Figure 7.2 FS CLK Relationship to Receive Data and Control Signals
7.3
Clock and Data Recovery Circuit
This block consists of the Clock and Data Recovery Circuit and the Elasticity Buffer. The Elasticity Buffer is used to compensate for differences between the transmitting and receiving clock domains. The USB 2.0 specification defines a maximum clock error of 1000ppm of drift.
7.4
TX Logic
This block receives parallel data bytes placed on the DATA bus and performs the necessary transmit operations. These operations include parallel to serial conversion, bit stuffing and NRZI encoding. Upon valid assertion of the proper TX control lines by the SIE and TX State Machine, the TX LOGIC block will synchronously shift, at either the FS or HS rate, the data to the FS/HS TX block to be transmitted on the USB cable. Data transmit timing is shown in Figure 7.3.
Figure 7.3 Transmit Timing for a Data Packet
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The behavior of the Transmit State Machine is described below. Asserting a RESET forces the transmit state machine into the Reset state which negates TXREADY. When RESET is negated the transmit state machine will enter a wait state. The SIE asserts TXVALID to begin a transmission. After the SIE asserts TXVALID it can assume that the transmission has started when it detects TXREADY has been asserted. The SIE must assume that the USB3280 has consumed a data byte if TXREADY and TXVALID are asserted on the rising edge of CLKOUT. The SIE must have valid packet information (PID) asserted on the DATA bus coincident with the assertion of TXVALID. TXREADY is sampled by the SIE on the rising edge of CLKOUT. The SIE negates TXVALID to complete a packet. Once negated, the transmit logic will never reassert TXREADY until after the EOP has been generated. (TXREADY will not re-assert until TXVALD asserts again. The USB3280 is ready to transmit another packet immediately, however the SIE must conform to the minimum inter-packet delays identified in the USB 2.0 specification.
7.5
RX Logic
This block receives serial data from the CRC block and processes it to be transferred to the SIE on the DATA bus. The processing involved includes NRZI decoding, bit unstuffing, and serial to parallel conversion. Upon valid assertion of the proper RX control lines by the RX State Machine, the RX Logic block will provide bytes to the DATA bus as shown in the figures below. The behavior of the Receive State Machine is described below.
Figure 7.4 Receive Timing for Data with Unstuffed Bits The assertion of RESET will force the Receive State Machine into the Reset state. The Reset state deasserts RXACTIVE and RXVALID. When the RESET signal is deasserted the Receive State Machine enters the RX Wait state and starts looking for a SYNC pattern on the USB. When a SYNC pattern is detected the state machine will enter the Strip SYNC state and assert RXACTIVE. The length of the received Hi-Speed SYNC pattern varies and can be up to 32 bits long or as short as 12 bits long when at the end of five hubs. As a result, the state machine may remain in the Strip SYNC state for several byte times before capturing the first byte of data and entering the RX Data state. After valid serial data is received, the state machine enters the RX Data state, where the data is loaded into the RX Holding Register on the rising edge of CLKOUT and RXVALID is asserted. The SIE must clock the data off the DATA bus on the next rising edge of CLKOUT. If OPMODE = Normal, then stuffed bits are stripped from the data stream. Each time 8 stuffed bits are accumulated the state machine will enter the RX Data Wait state, negating RXVALID thus skipping a byte time.
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When the EOP is detected the state machine will enter the Strip EOP state and negate RXACTIVE and RXVALID. After the EOP has been stripped the Receive State Machine will reenter the RX Wait state and begin looking for the next packet. The behavior of the Receive State Machine is described below: RXACTIVE and RXREADY are sampled on the rising edge of CLKOUT. In the RX Wait state the receiver is always looking for SYNC. The USB3280 asserts RXACTIVE when SYNC is detected (Strip SYNC state). The USB3280 negates RXACTIVE when an EOP is detected and the elasticity buffer is empty (Strip EOP state). When RXACTIVE is asserted, RXVALID will be asserted if the RX Holding Register is full. RXVALID will be negated if the RX Holding Register was not loaded during the previous byte time. This will occur if 8 stuffed bits have been accumulated. The SIE must be ready to consume a data byte if RXACTIVE and RXVALID are asserted (RX Data state). Figure 7.5 shows the timing relationship between the received data (DP/DM), RXVALID, RXACTIVE, RXERROR and DATA signals. Notes: The USB 2.0 Transceiver does NOT decode Packet ID's (PIDs). They are passed to the SIE for decoding. Figure 7.5, Figure 7.6 and Figure 7.7 are timing examples of a HS/FS PHY when it is in HS mode. When a HS/FS PHY is in FS Mode there are approximately 40 CLKOUT cycles every byte time. The Receive State Machine assumes that the SIE captures the data on the DATA bus if RXACTIVE and RXVALID are asserted. In FS mode, RXVALID will only be asserted for one CLKOUT per byte time. In Figure 7.5, Figure 7.6 and Figure 7.7 the SYNC pattern on DP/DM is shown as one byte long. The SYNC pattern received by a device can vary in length. These figures assume that all but the last 12 bits have been consumed by the hubs between the device and the host controller.
Figure 7.5 Receive Timing for a Handshake Packet (no CRC)
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Figure 7.6 Receive Timing for Setup Packet
Figure 7.7 Receive Timing for Data Packet (with CRC-16) The receivers connect directly to the USB cable. The block contains a separate differential receiver for HS and FS mode. Depending on the mode, the selected receiver provides the serial data stream through the mulitplexer to the RX Logic block. The FS mode section of the FS/HS RX block also consists of a single-ended receiver on each of the data lines to determine the correct FS LINESTATE. For HS mode support, the FS/HS RX block contains a squelch circuit to insure that noise is never interpreted as data.
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7.6
USB 2.0 Transceiver
The SMSC Hi-Speed USB 2.0 Transceiver consists of the High Speed and Full Speed Transceivers, and the Termination resistors.
7.6.1
High Speed and Full Speed Transceivers
The USB3280 transceiver meets all requirements in the USB 2.0 specification. The receivers connect directly to the USB cable. This block contains a separate differential receiver for HS and FS mode. Depending on the mode, the selected receiver provides the serial data stream through the multiplexer to the RX Logic block. The FS mode section of the FS/HS RX block also consists of a single-ended receiver on each of the data lines to determine the correct FS linestate. For HS mode support, the FS/HS RX block contains a squelch circuit to insure that noise is never interpreted as data. The transmitters connect directly to the USB cable. The block contains a separate differential FS and HS transmitter which receive encoded, bit stuffed, serialized data from the TX Logic block and transmit it on the USB cable.
7.6.2
Termination Resistors
The USB3280 transceiver fully integrates all of the USB termination resistors. The USB3280 includes the 1.5k pull-up resistor on DP. In addition the 45 high speed termination resistors are also integrated. These integrated resistors require no tuning or trimming. The state of the resistors is determined by the operating mode of the PHY. The possible valid resistor combinations are shown in Table 7.1. RPU_DP_EN activates the 1.5k DP pull-up resistor HSTERM_EN activates the 45 DP and DM high speed termination resistors
Table 7.1 DP/DM termination vs. Signaling Mode
UTMI+ INTERFACE SETTINGS TERMSELECT XCVRSELECT OPMODE[1:0] RESISTOR SETTINGS HSTERM_EN 0b 0b 0b 1b 0b 0b 0b 1b RPU_DP_EN 0b 0b 1b 0b 1b 1b 1b 0b
SIGNALING MODE Tri-State Drivers Power-up Peripheral Chirp Peripheral HS Peripheral FS Peripheral HS/FS Suspend Peripheral HS/FS Resume Peripheral Test J/Test K Xb 1b 0b 0b 1b 1b 1b 0b
Xb 0b 1b 0b 1b 1b 1b 0b
01b 00b 10b 00b 00b 00b 10b 10b
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7.6.3
Bias Generator
This block consists of an internal bandgap reference circuit used for generating the high speed driver currents and the biasing of the analog circuits. This block requires an external 12k, 1% tolerance, external reference resistor connected from RBIAS to ground.
7.7
Crystal Oscillator and PLL
The USB3280 uses an internal crystal driver and PLL sub-system to provide a clean 480MHz reference clock that is used by the PHY during both transmit and receive. The USB3280 requires a clean 24MHz crystal or clock as a frequency reference. If the 24MHz reference is noisy or off frequency the PHY may not operate correctly. The USB3280 can use either a crystal or an external clock oscillator for the 24MHz reference. The crystal is connected to the XI and XO pins as shown in the application diagram, Figure 8.9. If a clock oscillator is used the clock should be connected to the XI input and the XO pin left floating. When a external clock is used the XI pin is designed to be driven with a 0 to 3.3 volt signal. When using an external clock the user needs to take care to ensure the external clock source is clean enough to not degrade the high speed eye performance. Once, the 480MHz PLL has locked to the correct frequency it will drive the CLKOUT pin with a 60MHz clock.
7.8
Internal Regulators and POR
The USB3280 includes an integrated set of built in power management functions. These power management features include a POR generation and allow the USB3280 to be powered from a single 3.3 volt power supply. This reduces the bill of materials and simplifies product design.
7.8.1
Internal Regulators
The USB3280 has two integrated 3.3 volt to 1.8 volt regulators. These regulators require an external 4.7uF +/-20% low ESR bypass capacitor to ensure stability. X5R or X7R ceramic capacitors are recommended since they exhibit an ESR lower than 0.1 ohm at frequencies greater than 10kHz. The two regulator outputs, which require bypass capacitors, are the pins labeled VDDA1.8 and VDD1.8. Each pin requires a 4.7uF bypass capacitor placed as close to the pin as possible. Note: The USB3280 regulators are designed to generate a 1.8 volt supply for the USB3280 only. Using the regulators to provide current for other circuits is not recommended and SMSC does not guarantee USB performance or regulator stability.
7.8.2
Power On Reset (POR)
The USB3280 provides an internal POR circuit that generates a reset pulse once the PHY supplies are stable. The UTMI+ Digital can be reset at any time with the RESET pin.
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Chapter 8 Application Notes
The following sections consist of select functional explanations to aid in implementing the USB3280 into a system. For complete description and specifications consult the USB 2.0 Transceiver Macrocell Interface Specification and Universal Serial Bus Specification Revision 2.0.
8.1
Linestate
The voltage thresholds that the LINESTATE[1:0] signals use to reflect the state of DP and DM depend on the state of XCVRSELECT. LINESTATE[1:0] uses HS thresholds when the HS transceiver is enabled (XCVRSELECT = 0) and FS thresholds when the FS transceiver is enabled (XCVRSELECT = 1). There is not a concept of variable single-ended thresholds in the USB 2.0 specification for HS mode. The HS receiver is used to detect Chirp J or K, where the output of the HS receiver is always qualified with the Squelch signal. If squelched, the output of the HS receiver is ignored. In the USB3280, as an alternative to using variable thresholds for the single-ended receivers, the following approach is used. Table 8.1 Linestate States STATE OF DP/DM LINES LINESTATE[1:0] LS[1] 0 0 LS[0] 0 1 FULL SPEED XCVRSELECT =1 TERMSELECT=1 SE0 J HIGH SPEED XCVRSELECT =0 TERMSELECT=0 Squelch !Squelch CHIRP MODE XCVRSELECT =0 TERMSELECT=1 Squelch !Squelch & HS Differential Receiver Output !Squelch & !HS Differential Receiver Output Invalid
1
0
K
Invalid
1
1
SE1
Invalid
In HS mode, 3ms of no USB activity (IDLE state) signals a reset. The SIE monitors LINESTATE[1:0] for the IDLE state. To minimize transitions on LINESTATE[1:0] while in HS mode, the presence of !Squelch is used to force LINESTATE[1:0] to a J state.
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8.2
OPMODES
The OPMODE[1:0] pins allow control of the operating modes. Table 8.2 Operational Modes
MODE[1:0] 00 01
STATE# 0 1
STATE NAME Normal Operation Non-Driving
DESCRIPTION Transceiver operates with normal USB data encoding and decoding Allows the transceiver logic to support a soft disconnect feature which tri-states both the HS and FS transmitters, and removes any termination from the USB making it appear to an upstream port that the device has been disconnected from the bus Disables bitstuffing and NRZI encoding logic so that 1's loaded from the DATA bus become 'J's on the DP/DM and 0's become 'K's N/A
10
2
Disable Bit Stuffing and NRZI encoding Reserved
11
3
The OPMODE[1:0] signals are normally changed only when the transmitter and the receiver are quiescent, i.e. when entering a test mode or for a device initiated resume. When using OPMODE[1:0] = 10 (state 2), OPMODES are set, and then 5 60MHz clocks later, TXVALID is asserted. In this case, the SYNC and EOP patterns are not transmitted. The only exception to this is when OPMODE[1:0] is set to state 2 while TXVALID has been asserted (the transceiver is transmitting a packet), in order to flag a transmission error. In this case, the USB3280 has already transmitted the SYNC pattern so upon negation of TXVALID the EOP must also be transmitted to properly terminate the packet. Changing the OPMODE[1:0] signals under all other conditions, while the transceiver is transmitting or receiving data will generate undefined results. Under no circumstances should the device controller change OPMODE while the DP/DM lines are still transmitting or unpredictable changes on DP/DM are likely to occur. The same applies for TERMSELECT and XCVRSELECT.
8.3
Test Mode Support
Table 8.3 USB 2.0 Test Modes USB3280 SETUP XCVRSELECT & TERMSELECT HS HS HS HS
USB 2.0 TEST MODES SE0_NAK J K Test_Packet
OPERATIONAL MODE State 0 State 2 State 2 State 0
SIE TRANSMITTED DATA No transmit All '1's All '0's Test Packet data
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8.4
SE0 Handling
For FS operation, IDLE is a J state on the bus. SE0 is used as part of the EOP or to indicate reset. When asserted in an EOP, SE0 is never asserted for more than 2 bit times. The assertion of SE0 for more than 2.5us is interpreted as a reset by the device operating in FS mode. For HS operation, IDLE is a SE0 state on the bus. SE0 is also used to reset a HS device. A HS device cannot use the 2.5us assertion of SE0 (as defined for FS operation) to indicate reset since the bus is often in this state between packets. If no bus activity (IDLE) is detected for more than 3ms, a HS device must determine whether the downstream facing port is signaling a suspend or a reset. The following section details how this determination is made. If a reset is signaled, the HS device will then initiate the HS Detection Handshake protocol.
8.5
Reset Detection
If a device in HS mode detects bus inactivity for more than 3ms (T1), it reverts to FS mode. This enables the FS pull-up on the DP line in an attempt to assert a continuous FS J state on the bus. The SIE must then check LINESTATE for the SE0 condition. If SE0 is asserted at time T2, then the upstream port is forcing the reset state to the device (i.e., a Driven SE0). The device will then initiate the HS detection handshake protocol.
Figure 8.1 Reset Timing Behavior (HS Mode) Table 8.4 Reset Timing Values (HS Mode) TIMING PARAMETER HS Reset T0 T1 T2
DESCRIPTION Bus activity ceases, signaling either a reset or a SUSPEND. Earliest time at which the device may place itself in FS mode after bus activity stops. SIE samples LINESTATE. If LINESTATE = SE0, then the SE0 on the bus is due to a Reset state. The device now enters the HS Detection Handshake protocol. 0 (reference)
VALUE
HS Reset T0 + 3. 0ms < T1 < HS Reset T0 + 3.125ms T1 + 100s < T2 < T1 + 875s
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8.6
Suspend Detection
If a HS device detects SE0 asserted on the bus for more than 3ms (T1), it reverts to FS mode. This enables the FS pull-up on the DP line in an attempt to assert a continuous FS J state on the bus. The SIE must then check LINESTATE for the J condition. If J is asserted at time T2, then the upstream port is asserting a soft SE0 and the USB is in a J state indicating a suspend condition. By time T4 the device must be fully suspended.
Figure 8.2 Suspend Timing Behavior (HS Mode) Table 8.5 Suspend Timing Values (HS Mode) TIMING PARAMETER HS Reset T0 T1 T2
DESCRIPTION End of last bus activity, signaling either a reset or a SUSPEND. The time at which the device must place itself in FS mode after bus activity stops. SIE samples LINESTATE. If LINESTATE = 'J', then the initial SE0 on the bus (T0 - T1) had been due to a Suspend state and the SIE remains in HS mode. The earliest time where a device can issue Resume signaling. The latest time that a device must actually be suspended, drawing no more than the suspend current from the bus. 0 (reference)
VALUE
HS Reset T0 + 3. 0ms < T1 < HS Reset T0 + 3.125ms T1 + 100 s < T2 < T1 + 875s
T3 T4
HS Reset T0 + 5ms HS Reset T0 + 10ms
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8.7
HS Detection Handshake
The High Speed Detection Handshake process is entered from one of three states: suspend, active FS or active HS. The downstream facing port asserting an SE0 state on the bus initiates the HS Detection Handshake. Depending on the initial state, an SE0 condition can be asserted from 0 to 4 ms before initiating the HS Detection Handshake. These states are described in the USB 2.0 specification. There are three ways in which a device may enter the HS Handshake Detection process: 1. If the device is suspended and it detects an SE0 state on the bus it may immediately enter the HS handshake detection process. 2. If the device is in FS mode and an SE0 state is detected for more than 2.5s. it may enter the HS handshake detection process. 3. If the device is in HS mode and an SE0 state is detected for more than 3.0ms. it may enter the HS handshake detection process. In HS mode, a device must first determine whether the SE0 state is signaling a suspend or a reset condition. To do this the device reverts to FS mode by placing XCVRSELECT and TERMSELECT into FS mode. The device must not wait more than 3.125ms before the reversion to FS mode. After reverting to FS mode, no less than 100s and no more than 875s later the SIE must check the LINESTATE signals. If a J state is detected the device will enter a suspend state. If an SE0 state is detected, then the device will enter the HS Handshake detection process. In each case, the assertion of the SE0 state on the bus initiates the reset. The minimum reset interval is 10ms. Depending on the previous mode that the bus was in, the delay between the initial assertion of the SE0 state and entering the HS Handshake detection can be from 0 to 4ms. This transceiver design pushes as much of the responsibility for timing events on to the SIE as possible, and the SIE requires a stable CLKOUT signal to perform accurate timing. In case 2 and 3 above, CLKOUT has been running and is stable, however in case 1 the USB3280 is reset from a suspend state, and the internal oscillator and clocks of the transceiver are assumed to be powered down. A device has up to 6ms after the release of SUSPENDN to assert a minimum of a 1ms Chirp K.
8.8
HS Detection Handshake - FS Downstream Facing Port
Upon entering the HS Detection process (T0) XCVRSELECT and TERMSELECT are in FS mode. The DP pull-up is asserted and the HS terminations are disabled. The SIE then sets OPMODE to Disable Bit Stuffing and NRZI encoding, XCVRSELECT to HS mode, and begins the transmission of all 0's data, which asserts a HS K (chirp) on the bus (T1). The device chirp must last at least 1.0ms, and must end no later than 7.0ms after HS Reset T0. At time T1 the device begins listening for a chirp sequence from the host port. If the downstream facing port is not HS capable, then the HS K asserted by the device is ignored and the alternating sequence of HS Chirp K's and J's is not generated. If no chirps are detected (T4) by the device, it will enter FS mode by returning XCVRSELECT to FS mode.
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Figure 8.3 HS Detection Handshake Timing Behavior (FS Mode) Table 8.6 HS Detection Handshake Timing Values (FS Mode) TIMING PARAMETER T0 T1 T2 T3 T4 T5 Notes: T0 may occur to 4ms after HS Reset T0. The SIE must assert the Chirp K for 66000 CLKOUT cycles to ensure a 1ms minimum duration.
DESCRIPTION HS Handshake begins. DP pull-up enabled, HS terminations disabled. Device enables HS Transceiver and asserts Chirp K on the bus. Device removes Chirp K from the bus. 1ms minimum width. Earliest time when downstream facing port may assert Chirp KJ sequence on the bus. Chirp not detected by the device. Device reverts to FS default state and waits for end of reset. Earliest time at which host port may end reset 0 (reference)
VALUE
T0 < T1 < HS Reset T0 + 6.0ms T1 + 1.0 ms < T2 < HS Reset T0 + 7.0ms T2 < T3 < T2+100s T2 + 1.0ms < T4 < T2 + 2.5ms HS Reset T0 + 10ms
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8.9
HS Detection Handshake - HS Downstream Facing Port
Upon entering the HS Detection process (T0) XCVRSELECT and TERMSELECT are in FS mode. The DP pull-up is asserted and the HS terminations are disabled. The SIE then sets OPMODE to Disable Bit Stuffing and NRZI encoding, XCVRSELECT to HS mode, and begins the transmission of all 0's data, which asserts a HS K (chirp) on the bus (T1). The device chirp must last at least 1.0ms, and must end no later than 7.0ms after HS Reset T0. At time T1 the device begins listening for a chirp sequence from the downstream facing port. If the downstream facing port is HS capable then it will begin generating an alternating sequence of Chirp K's and Chirp J's (T3) after the termination of the chirp from the device (T2). After the device sees the valid chirp sequence Chirp K-J-K-J-K-J (T6), it will enter HS mode by setting TERMSELECT to HS mode (T7). Figure 8.4 provides a state diagram for Chirp K-J-K-J-K-J validation. Prior to the end of reset (T9) the device port must terminate the sequence of Chirp K's and Chirp J's (T8) and assert SE0 (T8-T9). Note that the sequence of Chirp K's and Chirp J's constitutes bus activity.
Start Chirp K-J-K-J-K-J detection Chirp Count =0
!K K State Detect K? Chirp Count != 6 & !SE0 !J J State Detect J? Chirp Count != 6 & !SE0 INC Chirp Count Chirp Count Chirp Valid INC Chirp Count SE0 Chirp Invalid
Figure 8.4 Chirp K-J-K-J-K-J Sequence Detection State Diagram The Chirp K-J-K-J-K-J sequence occurs too slow to propagate through the serial data path, therefore LINESTATE signal transitions must be used by the SIE to step through the Chirp K-J-K-J-K-J state diagram, where "K State" is equivalent to LINESTATE = K State and "J State" is equivalent to LINESTATE = J State. The SIE must employ a counter (Chirp Count) to count the number of Chirp K and Chirp J states. Note that LINESTATE does not filter the bus signals so the requirement that a bus state must be "continuously asserted for 2.5s" must be verified by the SIE sampling the LINESTATE signals.
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Figure 8.5 HS Detection Handshake Timing Behavior (HS Mode) Table 8.7 Reset Timing Values TIMING PARAMETER T0 T1 T2 T3 T4 T5 T6 T7
DESCRIPTION HS Handshake begins. DP pull-up enabled, HS terminations disabled. Device asserts Chirp K on the bus. Device removes Chirp K from the bus. 1 ms minimum width. Downstream facing port asserts Chirp K on the bus. Downstream facing port toggles Chirp K to Chirp J on the bus. Downstream facing port toggles Chirp J to Chirp K on the bus. Device detects downstream port chirp. Chirp detected by the device. Device removes DP pull-up and asserts HS terminations, reverts to HS default state and waits for end of reset. Terminate host port Chirp K-J sequence (Repeating T4 and T5) The earliest time at which host port may end reset. The latest time, at which the device may remove the DP pull-up and assert the HS terminations, reverts to HS default state. 0 (reference)
VALUE
T0 < T1 < HS Reset T0 + 6.0ms T0 + 1.0ms < T2 < HS Reset T0 + 7.0ms T2 < T3 < T2+100s T3 + 40s < T4 < T3 + 60s T4 + 40s < T5 < T4 + 60s T6 T6 < T7 < T6 + 500s
T8 T9
T9 - 500s < T8 < T9 - 100s HS Reset T0 + 10ms
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Notes: T0 may be up to 4ms after HS Reset T0. The SIE must use LINESTATE to detect the downstream port chirp sequence. Due to the assertion of the HS termination on the host port and FS termination on the device port, between T1 and T7 the signaling levels on the bus are higher than HS signaling levels and are less than FS signaling levels.
8.10
HS Detection Handshake - Suspend Timing
If reset is entered from a suspended state, the internal oscillator and clocks of the transceiver are assumed to be powered down. Figure 8.6 shows how CLKOUT is used to control the duration of the chirp generated by the device. When reset is entered from a suspended state (J to SE0 transition reported by LINESTATE), SUSPENDN is combinatorially negated at time T0 by the SIE. It takes approximately 5 milliseconds for the transceiver's oscillator to stabilize. The device does not generate any transitions of the CLKOUT signal until it is "usable" (where "usable" is defined as stable to within 10% of the nominal frequency and the duty cycle accuracy 505%). The first transition of CLKOUT occurs at T1. The SIE then sets OPMODE to Disable Bit Stuffing and NRZI encoding, XCVRSELECT to HS mode, and must assert a Chirp K for 66000 CLKOUT cycles to ensure a 1ms minimum duration. If CLKOUT is 10% fast (66MHz) then Chirp K will be 1.0ms. If CLKOUT is 10% slow (54 MHz) then Chirp K will be 1.2ms. The 5.6ms requirement for the first CLKOUT transition after SUSPENDN, ensures enough time to assert a 1ms Chirp K and still complete before T3. Once the Chirp K is completed (T3) the SIE can begin looking for host chirps and use CLKOUT to time the process. At this time, the device follows the same protocol as in Section 8.9, "HS Detection Handshake - HS Downstream Facing Port" for completion of the High Speed Handshake.
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T0 time
T1
T2
T3
T4
OPMODE 0 OPMODE 1 XCVRSELECT TERMSELECT SUSPENDN TXVALID CLK60 DP/DM
J SE0
CLK power up time
Device Chirp K
Look for host chirps
Figure 8.6 HS Detection Handshake Timing Behavior from Suspend
To detect the assertion of the downstream Chirp K's and Chirp J's for 2.5us {TFILT}, the SIE must see the appropriate LINESTATE signals asserted continuously for 165 CLKOUT cycles.
Table 8.8 HS Detection Handshake Timing Values from Suspend TIMING PARAMETER T0
DESCRIPTION While in suspend state an SE0 is detected on the USB. HS Handshake begins. D+ pull-up enabled, HS terminations disabled, SUSPENDN negated. First transition of CLKOUT. CLKOUT "Usable" (frequency accurate to 10%, duty cycle accurate to 505). Device asserts Chirp K on the bus. Device removes Chirp K from the bus. (1 ms minimum width) and begins looking for host chirps. CLK "Nominal" (CLKOUT is frequency accurate to 500 ppm, duty cycle accurate to 505).
VALUE 0 (HS Reset T0)
T1 T2 T3 T4
T0 < T1 < T0 + 5.6ms T1 < T2 < T0 + 5.8ms T2 + 1.0 ms < T3 < T0 + 7.0 ms T1 < T3 < T0 + 20.0ms
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8.11
Assertion of Resume
In this case, an event internal to the device initiates the resume process. A device with remote wakeup capability must wait for at least 5ms after the bus is in the idle state before sending the remote wake-up resume signaling. This allows the hubs to get into their suspend state and prepare for propagating resume signaling. The device has 10ms where it can draw a non-suspend current before it must drive resume signaling. At the beginning of this period the SIE may negate SUSPENDN, allowing the transceiver (and its oscillator) to power up and stabilize. Figure 8.7 illustrates the behavior of a device returning to HS mode after being suspended. At T4, a device that was previously in FS mode would maintain TERMSELECT and XCVRSELECT high. To generate resume signaling (FS 'K') the device is placed in the "Disable Bit Stuffing and NRZI encoding" Operational Mode (OPMODE [1:0] = 10), TERMSELECT and XCVRSELECT must be in FS mode, TXVALID asserted, and all 0's data is presented on the DATA bus for at least 1ms (T1 - T2).
Figure 8.7 Resume Timing Behavior (HS Mode) Table 8.9 Resume Timing Values (HS Mode) TIMING PARAMETER T0 T1 T2
DESCRIPTION Internal device event initiating the resume process Device asserts FS 'K' on the bus to signal resume request to downstream port The device releases FS 'K' on the bus. However by this time the 'K' state is held by downstream port. Downstream port asserts SE0. Latest time at which a device, which was previously in HS mode, must restore HS mode after bus activity stops. 0 (reference)
VALUE
T0 < T1 < T0 + 10ms. T1 + 1.0ms < T2 < T1 + 15ms
T3 T4
T1 + 20ms T3 + 1.33s {2 Low-speed bit times}
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8.12
Detection of Resume
Resume signaling always takes place in FS mode (TERMSELECT and XCVRSELECT = FS enabled), so the behavior for a HS device is identical to that of a FS device. The SIE uses the LINESTATE signals to determine when the USB transitions from the 'J' to the 'K' state and finally to the terminating FS EOP (SE0 for 1.25us-1.5s.). The resume signaling (FS 'K') will be asserted for at least 20ms. At the beginning of this period the SIE may negate SUSPENDN, allowing the transceiver (and its oscillator) to power up and stabilize. The FS EOP condition is relatively short. SIEs that simply look for an SE0 condition to exit suspend mode do not necessarily give the transceiver's clock generator enough time to stabilize. It is recommended that all SIE implementations key off the 'J' to 'K' transition for exiting suspend mode (SUSPENDN = 1). And within 1.25s after the transition to the SE0 state (low-speed EOP) the SIE must enable normal operation, i.e. enter HS or FS mode depending on the mode the device was in when it was suspended. If the device was in FS mode: then the SIE leaves the FS terminations enabled. After the SE0 expires, the downstream port will assert a J state for one low-speed bit time, and the bus will enter a FS Idle state (maintained by the FS terminations). If the device was in HS mode: then the SIE must switch to the FS terminations before the SE0 expires ( < 1.25s). After the SE0 expires, the bus will then enter a HS IDLE state (maintained by the HS terminations).
8.13
HS Device Attach
Figure 8.8 demonstrates the timing of the USB3280 control signals during a device attach event. When a HS device is attached to an upstream port, power is asserted to the device and the device sets XCVRSELECT and TERMSELECT to FS mode (time T1). VBUS is the +5V power available on the USB cable. Device Reset in Figure 8.8 indicates that VBUS is within normal operational range as defined in the USB 2.0 specification. The assertion of Device Reset (T0) by the upstream port will initialize the device. By monitoring LINESTATE, the SIE state machine knows to set the XCVRSELECT and TERMSELECT signals to FS mode (T1). The standard FS technique of using a pull-up resistor on DP to signal the attach of a FS device is employed. The SIE must then check the LINESTATE signals for SE0. If LINESTATE = SE0 is asserted at time T2 then the upstream port is forcing the reset state to the device (i.e. Driven SE0). The device will then reset itself before initiating the HS Detection Handshake protocol.
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Figure 8.8 Device Attach Behavior Table 8.10 Attach and Reset Timing Values TIMING PARAMETER T0 T1 T2 (HS Reset T0) Vbus Valid. Maximum time from Vbus valid to when the device must signal attach. Debounce interval. The device now enters the HS Detection Handshake protocol.
DESCRIPTION 0 (reference)
VALUE
T0 + 100ms < T1 T1 + 100ms < T2
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8.14
Application Diagram
UTMI TXVALID TXREADY RXACTIVE RXVALID RXERROR 26 25 24 23 22 21 20 19 DATA DATA DATA DATA DATA DATA DATA DATA 0 1 2 3 4 5 6 7 5 3 11 27 28
1 XCVRSELECT 2 TERMSELECT 4 SUSPENDN 6 RESET 13 OPMODE 0 12 OPMODE 1 16 LINESTATE 0 15 LINESTATE 1 CLKOUT USB RBIAS DP DM POWER 14 36 8 12K USB-B
C
LOAD
32
1
XI XO
24 MHz Crystal
31
9
C
LOAD
33 VDDA1.8 4.7uF Ceramic 4.7uF Ceramic 17 VDD1.8 30 VDD1.8
4.7uF Ceramic
7 34 VDD3.3 35 VDD3.3 VDD3.3 10 VDD3.3 18 VDD3.3 29 VDD3.3
VDD3.3
VSS
Exposed Pad
0.1uF and/or 0.01uF ceramic capacitors are also required on power supply pins.
GND
Figure 8.9 USB3280 Application Diagram
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Chapter 9 Package Outline
REVISION HISTORY
REVISION DESCRIPTION INITIAL RELEASE ADDED "PRELIMINARY" NOTE DELETED "PRELIMINARY" NOTE NEW SMSC DRAWING FORMAT & ADDING 3-D VIEW L(MIN) FROM 0.35 TO 0.50, D2/E2 FROM 1.75 - 4.25 TO 3.55-3.70-3.85 ADDED PARAGRAPHS 1 TO 6 IN MAIN SPEC BODY & DWG AS ATTACHMENT DATE 6/13/03 11/6/03 6/30/04 12/7/04 4/5/05 7/11/05 RELEASED BY S.K.ILIEV S.K.ILIEV S.K.ILIEV S.K.ILIEV S.K.ILIEV S.K.ILIEV
Revision 1.2 (10-27-06) 42 DATASHEET SMSC USB3280
Datasheet
Hi-Speed USB Device PHY with UTMI Interface
D 3 TERMINAL #1 IDENTIFIER AREA (D1/2 X E1/2) D1 e
D2
A
TERMINAL #1 IDENTIFIER AREA (D/2 X E/2)
3
B C D E F
E1
E
E2
EXPOSED PAD 4
36X L
4X 45X0.6 MAX (OPTIONAL)
36X 0.2 MIN
36X b 2
TOP VIEW
BOTTOM VIEW
4X 0-12 C 4 ccc C A1 A3 A2 A
SIDE VIEW
D2 / E2 VARIATIONS CATALOG PART
3-D VIEWS
UNLESS OTHERWISE SPECIFIED DIMENSIONS ARE IN MILLIMETERS AND TOLERANCES ARE: DECIMAL X.X 0.1 X.XX 0.05 X.XXX 0.025 ANGULAR 1
THIRD ANGLE PROJECTION
80 ARKAY DRIVE HAUPPAUGE, NY 11788 USA
NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETER. 2. POSITION TOLERANCE OF EACH TERMINAL IS 0.05mm AT MAXIMUM MATERIAL CONDITION. DIMENSIONS "b" APPLIES TO PLATED TERMINALS AND IT IS MEASURED BETWEEN 0.15 AND 0.30 mm FROM THE TERMINAL TIP. 3. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL BUT MUST BE LOCATED WITHIN THE AREA INDICATED. 4. COPLANARITY ZONE APPLIES TO EXPOSED PAD AND TERMINALS.
TITLE
DIM AND TOL PER ASME Y14.5M - 1994
MATERIAL
NAME
DRAWN
DATE
-
S.K.ILIEV
CHECKED
12/6/04 12/6/04
PACKAGE OUTLINE 36 TERMINAL QFN, 6x6mm BODY, 0.5mm PITCH
DWG NUMBER
FINISH
S.K.ILIEV
APPROVED
MO-36-QFN-6x6
STD COMPLIANCE SHEET
REV
F 1 OF 1
PRINT WITH "SCALE TO FIT" DO NOT SCALE DRAWING
SCALE
S.K.ILIEV
12/6/04
1:1
JEDEC: MO-220
Figure 9.1 USB3280-AEZG 36-Pin QFN Package Outline and Parameters, 6 x 6 x 0.90 mm Body (Lead-Free RoHS Compliant)

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